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general description the max3980 quad equalizer provides compensation for transmission medium losses for four ?anes?of digi- tal nrz data at a 3.125gbps data rate in one package. it is tailor-made for 10-gigabit ethernet (10gbe) back- plane applications requiring attenuation of noise and jit- ter that occur in communicating from mac to pmd or from mac to switch. in support of the ieee-802.3ae for the xaui interface, the max3980 adaptively allows xaui lanes to reach up to 40in (1.0m) on fr4 board material. the equalizer has 100 ? differential cml data inputs and outputs. the max3980 is available in a 44-pin exposed-pad qfn package. the max3980 consumes only 700mw at +3.3v or 175mw per channel. applications ieee-802.3ae xaui interface (3.125gbps) infiniband (2.5gbps) features ? four differential digital data ?anes?at 3.125gbps ? spans 40in (1.0m) of fr4 pc board ? receiver equalization reduces intersymbol interference (isi) ? low-power, 175mw per channel ? standby mode?ower-down state ? single +3.3v supply ? signal detect max3980 3.125gbps xaui quad equalizer ________________________________________________________________ maxim integrated products 1 ordering information line card pmd mac rx rx tx tx rx rx tx tx 10gbe 4 4 4 4 4 4 4 x 3.125gbps 4 x 3.125gbps switch rx tx 40in (1.0m) switch card max3980 out in +3.3v supply max3980 in out +3.3v supply pc board backplane 40in (1.0m) typical application circuit 19-2153; rev 2; 1/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. evaluation kit available part temp range pin- package pkg code max3980ugh 0? to +85? 44 qfn g4477-1 max3980uth+ 0? to +85? 44 qfn t4477-3 + denotes lead-free package.
max3980 3.125gbps xaui quad equalizer 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3.0v to +3.6v, input data rate = 3.125gbps, t a = 0? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc .............................................-0.5v to +4.0 v voltage at sdet, in_ ..............................+0.5v to (v cc + 0.5v) current out of out_.......................................-25ma to +25ma continuous power dissipation (t a = +85?) 44-pin qfn-ep (derate 26.3mw/? above +85?)...2105mw operating ambient temperature range ................0? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units en = ttl low 0.25 supply power en = ttl high 0.7 0.9 w 10hz < f < 100hz 100 100hz < f < 1mhz 40 supply noise tolerance 1mhz < f < 2.5ghz 10 mvp-p signal detect assert input signal level to assert sdet (note 1) 100 mvp-p signal detect deassert input signal level to deassert sdet (note 1) 30 mvp-p signal detect delay 10 s latency from input to output 0.32 ns cml receiver input input voltage swing xaui transmitter output measured differentially at point a, figure 1, using k28.5 pattern 200 800 mvp-p return loss 100mhz to 2.5ghz 12 db input resistance differential 80 100 120 ? equalization total jitter (note 2) 0.3 residual jitter deterministic jitter 0.2 uip-p random jitter (note 2) 1.5 ps rms cml transmitter output (into 100 ? 1 ? ) output voltage swing differential swing 550 850 mvp-p common-mode voltage v cc - 0.3 v transition time t f , t r 20% to 80% (note 3) 60 130 ps differential skew difference in 50% crossing between out_+ and out_- 12 ps output resistance single ended 40 50 60 ?
max3980 3.125gbps xaui quad equalizer _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, input data rate = 3.125gbps, t a = 0? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units ttl control pins input high voltage 2.0 v input low voltage 0.8 v input high current 250 a input low current 500 a output high voltage internal 10k ? pullup 2.4 v output low voltage internal 10k ? pullup 0.4 v note 1: k28.7 pattern is applied differentially at point a as shown in figure 1. note 2: total jitter does not include the signal source jitter. total jitter (tj) = [14.1 x rj + dj] where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern ( 00 1111 1010 11 0000 0101 ) for the deterministic jitter test and k28.7 ( 0011111000 ) or equivalent for the random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media- induced loss and not from clock-source modulation. jitter is measured at 0 at point c of figure 1. note 3: using k28.7 ( 0011111000 ) pattern. out in sma connector sma connector 40in (1m) fr4 stripline a b c max3980 figure 1. test conditions referenced in the electrical characteristics table
max3980 3.125gbps xaui quad equalizer 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, 3.125gbps, 500mvp-p board input with 2 7 - 1 prbs, t a = +25?, unless otherwise noted.) 50mv/ div 50ps/div equalizer input eye diagram before equalization (40in fr4 6mil stripline) max3980 toc01 100mv/ div 50ps/div equalizer output eye diagram after equalization (40in fr4 6mil stripline) max3980 toc02 100mv/ div 50ps/div equalizer output eye diagram (20in backplane with two teradyne hsd connectors and 3in daughterboard) max3980 toc03 -50 -30 -40 -10 -20 0 10 50 input return gain (s11, differential, input signal = -60dbm, device powered off) max3980 toc04 frequency (mhz) gain (db) 2050 1050 3050 4050 5050 0 35 30 25 20 15 10 5 40 equalizer deterministic jitter vs. length (fr4 6mil stripline, k28.5 pattern) max3980 toc05 length (in) jitter (ps) 02030 10 40 50 200 250 300 350 400 450 500 020 10 30 40 50 60 70 80 90 equalizer latency vs. temperature max3980 toc06 temperature ( c) delay (ps) 70 50 130 110 90 170 190 150 210 03040 10 20 50 60 70 80 equalizer operating current vs. temperature max3980 toc07 temperature ( c) current (ma) normal operation (en = ttl high) standby power (en = ttl low)
max3980 3.125gbps xaui quad equalizer _______________________________________________________________________________________ 5 pin description pin name function 1, 5, 9, 13, 23, 27, 31, 35 v cc +3.3v supply voltage 2 in1+ positive equalizer input channel 1, cml 3 in1- negative equalizer input channel 1, cml 4, 8, 12, 16, 26, 30, 34, 38 gnd supply ground 6 in2+ positive equalizer input channel 2, cml 7 in2- negative equalizer input channel 2, cml 10 in3+ positive equalizer input channel 3, cml 11 in3- negative equalizer input channel 3, cml 14 in4+ positive equalizer input channel 4, cml 15 in4- negative equalizer input channel 4, cml 17?2, 39?2 n.c. no connection. leave unconnected. 24 out4- negative equalizer output channel 4, cml 25 out4+ positive equalizer output channel 4, cml 28 out3- negative equalizer output channel 3, cml 29 out3+ positive equalizer output channel 3, cml 32 out2- negative equalizer output channel 2, cml 33 out2+ positive equalizer output channel 2, cml 36 out1- negative equalizer output channel 1, cml 37 out1+ positive equalizer output channel 1, cml 43 en enable equalizer input. a ttl high selects normal operation. a ttl low selects low-power standby mode. 44 sdet signal detect output for channel 1. produces a ttl high output when a signal is detected. ep exposed pad ground. the exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance.
max3980 detailed description receiver and transmitter the receiver accepts four lanes of 3.125gbps current- mode logic (cml) digital data signals. the adaptive equalizer compensates each received signal for dielec- tric and skin losses. the limiting amp shapes the output of the equalizer. the regenerated xaui lanes are trans- mitted as cml signals. the source impedance and ter- mination impedances are 100 ? differential. general theory of operation internally, the max3980 comprises signal-detect cir- cuitry, four matched equalizers, and one equalizer- control loop. the four equalizers are made up of a mas- ter equalizer and three slave equalizers. the adaptive control is generated from only channel 1. it is assumed that all channels have the same characterization in fre- quency content, coding, and transmission length. the master equalizer consists of the following functions: signal detect, adaptive equalizer, equalizer control, and limiting and output drivers. the signal detect indicates input signal power. when the input signal level is suffi- ciently high, the sdet output is asserted. this does not directly control the operation of the part. the equalizer core reduces intersymbol interference (isi), compensating for frequency-dependent, media- induced loss. the equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to dif- ferent media. the equalizer operation is optimized for short-run dc-balanced transmission codes such as 8b/10b codes. cml input and output buffers the input and output buffers are implemented using cml. equivalent circuits are shown in figures 2 and 3. for details on interfacing with cml, see maxim applica- tion note hfan-1.0, interfacing between cml, pecl, and lvds . the common-mode voltage of the input and output is above 2.5v. ac-coupling capacitors are required when interfacing this part. values of 0.10? or greater are recommended. media equalization equalization at the input port compensates for the high- frequency loss encountered with up to 40in (1.0m) of fr4 transmission lines. this part is optimized for 40in and 3.125gbps; however, the part reduces isi for sig- nals spanning longer distances and functions for data rates from 2gbps to 4gbps, provided that short-length balanced codes, such as 8b/10b, are used. applications information standby mode the power-saver standby state allows reduced-power operation. the ttl input, en, must be set to ttl high for normal operation. a ttl low at en forces the equal- izer into the standby state. the signal en does not affect the operation of the signal detect (sdet) func- tion. for constant operation, connect the en signal directly to v cc . 3.125gbps xaui quad equalizer 6 _______________________________________________________________________________________ functional diagram in1+ in1- equalizer limiting amp 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 out1+ out1- 2 3 4 2 3 4 en power management sdet function is independent of en sdet ttl cml signal detect ip1, in1 only max3980
signal detect with standby mode signal activity is detected on channel 1 only. when the peak-to-peak differential voltage at in1 is less than 30mvp-p, the ttl output sdet goes low. when the peak-to-peak differential voltage becomes greater than 100mvp-p, sdet is asserted high. sdet can be used to automatically force the equalizer into standby mode by connecting sdet directly to the en input. when not used, sdet should not be connected. the signal-detect function continues to operate while the part is in standby mode. while connected to the en pin, the signal detect can ?ake up?the part and resume normal operation. layout considerations circuit-board layout and design can significantly affect the max3980 performance. use good high-frequency design techniques, including minimizing ground induc- tances and vias and using controlled-impedance trans- mission lines for the high-frequency data signals. signals should be routed differentially to reduce emi susceptibility and crosstalk. power-supply decoupling capacitors should be placed as close as possible to the v cc pins. max3980 3.125gbps xaui quad equalizer _______________________________________________________________________________________ 7 v cc 1.2k ? 50 ? 50 ? 200 a in+ in- esd structures figure 2. cml input buffer 50 ? 50 ? v cc q1 q2 out+ out- data esd structures figure 3. cml output buffer out2+ out2- gnd out3+ gnd out4+ out4- v cc out3- v cc v cc in1- gnd v cc in2+ in2- gnd v cc in3+ in3- in1+ v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 gnd n.c. n.c. n.c. n.c. n.c. in4- in4+ v cc gnd en n.c. n.c. n.c. n.c. gnd out1+ out1- v cc gnd sdet max3980 n.c. top view * note: the exposed pad must be soldered to supply ground. qfn* pin configuration
max3980 3.125gbps xaui quad equalizer 8 _______________________________________________________________________________________ 32, 44, 48l qfn.eps h 1 2 21-0092 package outline 32,44,48l qfn, 7x7x0.90 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3980 3.125gbps xaui quad equalizer _______________________________________________________________________________________ 9 u h 2 2 21-0092 package outline, 32,44,48l qfn, 7x7x0.90 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3980 3.125gbps xaui quad equalizer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1 proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max3980 part number table notes: see the max3980 quickview data sheet for further information on this product family or download the max3980 full data sheet (pdf, 668kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max3980ugh-d qfn;44 pin;7x7x0.9mm dwg: 21-0092h (pdf) use pkgcode/variation: g4477-1 * -40c to +85c rohs/lead-free: no materials analysis MAX3980UGH-TD qfn;44 pin;7x7x0.9mm dwg: 21-0092h (pdf) use pkgcode/variation: g4477-1 * -40c to +85c rohs/lead-free: no materials analysis max3980uth+ thin qfn;44 pin;7x7x0.8mm dwg: 21-0144f (pdf) use pkgcode/variation: t4477+3 * -40c to +85c rohs/lead-free: yes materials analysis max3980uth+t thin qfn;44 pin;7x7x0.8mm dwg: 21-0144f (pdf) use pkgcode/variation: t4477+3 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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